Area Optimized High Throughput IDMWT/DMWT Processor for OFDM on Virtex-5 FPGA

OFDM is one of the most popular modulation techniques that is been widely used in most of the wireless and wired communication links. The OFDM architecture consists of QAM modulator and orthogonal frequency modulator. In this work we propose DMWT based orthogonal frequency modulator for achieving higher BER. The IDMWT architecture is designed considering N=4, thus the preprocessing unit converts the QAM samples of N to 2N and is modulated using DMWT filters. The filtered output is further transmitted and is received at the receiver. During the post processing, N samples are extracted by use of DMWT demodulation technique. The complex architecture of IDMWT and DMWT are reduced for its complexity and speed by the modified architecture. The DMWT architecture is modified for FPGA implementation improving the area, power and speed performances. The modified DMWT architecture is implemented on VirtexII pro FPGA which operates at 300MHz frequency and occupies area of less than 1%, with power consumption less than 28mW. The proposed design is suitable for real time and low power applications.