Optimising digital combinational circuit using particle swarm optimisation technique

Human methods of circuit minimisation are tedious and limited to systems with four or five numbers of inputs. In order to save time and labour involved in designing digital combinational logic circuit, a standard algorithm that is suitable for digital combinational logic circuit with little modification which handle circuit with more than five inputs variables is developed. Employing MATLAB, the circuits were coded into particles using Particle Swarm Optimisation (PSO) techniques. This was then used to optimise a full-adder circuit. The result obtained, after optimisation for full-adder circuit using PSO technique is shown to have a minimum number of gates (five gates) compared to human designermethod which has six gates.