DESIGN AND IMPLEMENTATION OF 120 ORDER FIR FILTER BASED ON FPGA

Distributed algorithm is suitable for FPGA to do multiply-accumulate operations, which use the abundant memory resources of FPGA to do look-up table operation. We present a method for implementing high speed Finite Impulse Response (FIR) filters using just registered adders and hardwired shifts. We extensively use a modified common sub expression elimination algorithm to reduce the number of adders. We target our optimizations to ALTERA devices we can save up to 50% reduction in the number of slices for fully parallel implementations. We can also achieve power reduction in the total power consumption of the filters. we presented a multiplier less technique, based on the add and shift method and common sub expression elimination for low area, low power and high speed implementations of FIR filters where we observed significant area and power reductions over traditional Distributed Arithmetic based techniques. Our designs perform significantly faster than the existing filters, which use embedded multipliers. The proposed technique efficiently generates adder graphs for the entire set of fixed coefficient by reusing common adder graphs and the partial sums as much as possible in order to reduce the hardware complexity and latency to implement FIR Filter. The multiplier-less method is based on the replacement of multiplications with a minimum number of additions and shifts. The proposed method is performed and compared to a previous one. The results of FPGA implementations on Altera Cyclone II show the increase of the maximum frequency, the decrease of the resources usage and the reduction of the dynamic power with a new proposed FGA algorithm. Another comparison with recent published results has been done and proves the efficiency of the proposed.