A HIGHLY TIME-EFFICIENT DIGITAL MULTIPLIER BASED ON THE A2 BINARY REPRESENTATION

A comparative study of different types of digital multipliers based on the A2 redundant binary representation is investigated in this paper. Some techniques have been proposed and implemented using different ALTERA Stratix FPGA platforms. The principle is to try to reduce the number of partial products terms to be summed with addition trees. These techniques are based on exploiting the associative and commutative properties of the addition operation. The multiplication was achieved using four schemes which are respectively the trivial scheme, the BRAUN scheme, the BOOTH scheme and finally the Carry-Save Wallace scheme. Two input A2- Natural transcoders and one output Natural-A2 transcoder are deployed to translate between the classical and the new A2 redundant binary representation. Synthesis results show that the A2-BRAUN multiplier requires lessarea than the conventional one. It was also noticed that the A2-Wallace multiplier offers better speed performance with respect to others schemes.