ARRAY MULTIPLIER USING XNORXOR CELL

The multipliers are the key structure for designing high performance digital systems. Design considerations of multiplier include high speed, less power consumption, less PDP (power-delay product) and regularity of layout. These design parameters make it suitable for various compact low power VLSI implementations. This paper presents an application of the proposed XNOR-XOR cell for a 2x2 array multiplier and its performance has been analyzed and compared in terms of power consumption and PDP with varying input voltage, temperature and frequency as compared to the existing XNOR-XOR cell based 2x2 array multiplier. All pre-layout and postlayout simulations have been performed at 45nm technology on Tanner EDA tool version 12.6.