Design and ASIC Implementation of a 3GPP LTEAdvance Turbo Encoder and Turbo Decoder

This paper presents the design and development of an efficient VLSI architecture for 3GPP advanced Turbo decoder by utilizing the convolutionalinterleaver. The high-throughput 3GPP Advance Turbocode requires turbo decoder architecture. Interleaver is known to be the main obstacle to the decoder implementation and introduces latency, due to the collisions it introduces in accesses to memory. In this paper, we propose a low-complexity Soft Input Soft Output (SISO) turbo decoder for memory architecture to enable the Turbo decoding that achieves minimum latency. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed Turbo decoder has been modeled using Simulink; various test cases are used to estimate the performances. The results are analyzed andachieved 50% reduction in computation time along with reduced BER (e-3). The hardware of the Turbo Encoder and Turbo Decoder has been modeled in Verilog, simulated in Modelsim, synthesized using TSMC 65 nm Synopsys Design compiler and physical implementation has been carried out using IC Compiler.