Efficient Implementation of Low Density Parity Check (LDPC) Decoder In VLSI

The best error-correcting performance can be achieved by using non-binary low-density parity check (NB-LDPC) codes. This can be of reduced decoding complexity with high cost efficiency and is mostly preferable than binary low density parity check codes. The proposed scheme not only reduces the computation complexity, but also eliminates the memory requirement for storing the intermediate messages generated from the forward and backward processes. A novel scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In the design, layered decoding is applied and only nm Keywords Low-density parity check codes(LDPC) --- latency --- Tanner graph --- check node processing --- sorter --- path constructor