Simulation of Nine level Cascaded H-bridge Multilevel DC-Link Inverter

This paper presents simulation of the nine level cascaded H-bridge multilevel inverter based on a multilevel DC link (MLDCL) and a bridge inverter to reduce the number of switches. An MLDCL can be a diode-clamped phase leg, a flying-capacitor phase leg, or cascaded half-bridge cells with each cell having its own DC source. Compared to diode clamped & flying capacitor type MLDCL inverters cascaded H-bridge multilevel inverter requires least no of components to achieve same no of voltage levels. Optimized circuit layout is possible because each level have same structure and there is no extra clamping diodes or capacitors. Soft switching techniques can also be used to reduce switching losses and device stresses. The MLDCL provides a DC voltage with the shape of a staircase approximating the rectified shape of a commanded sinusoidal wave to the bridge inverter, which in turn alternates the polarity to produce an AC voltage. Compared with the existing type of cascaded H-bridge multilevel inverter, the MLDCL inverters can significantly reduce the switch count as well as the number of gate drivers as the number of voltage levels increases. For a given number of voltage levels, the required number of active switches is 2 (m-1) for the existing multilevel inverters, but it is m+3 for the MLDCL inverters. This paper aims to present analysis and simulation of cascaded H bridge multilevel dc link inverter. Matlab simulation has been done and simulation results of the cascaded H-bridge MLDCL inverter supplying induction motor load is discussed and it is proved that proposed inverter output has less THD compared to flying capacitor and diode clamped multilevel inverter.