CMOS Design of a High-Speed 1T1C DRAM

This paper presents a new structure of DRAM, using two-transistors. The most important advantages of this structure are high speed read, write and refresh operation. We will focus on the layout consideration to reach a very compact structure compared with other works. The proposed DRAM is designed in a 0.35μm CMOS process, and then extracted layout file, simulated by HSPICE using level 49 parameters (BSIM3v3). Comparison between this work and other approaches confirm that this structure is better than conventional works in terms of operation speed.