Influence of HALO and Source/Drain Implantation Variations on Threshold Voltage in 45nm CMOS Technology

In this paper, we investigate the influence of process parameters such as HALO and Source/Drain (S/D) Implantation on threshold voltage (VTH) in Complementary Metal Oxide Semiconductor (CMOS) technology using Taguchi Method. The level of importance of the process parameters on VTH were determined by using analysis of variance. The fabrication of the transistor device was performed by using fabrication simulator of ATHENA. The electrical characterization of the device was implemented by using electrical characterization simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing the process parameters. The other two process parameters in this research are oxide growth temperature and silicide anneal temperature. Whereas, the two noise factors are sacrificial oxide temperature and annealing process temperature. Each of the noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. In NMOS and PMOS devices, the major factor affecting the threshold voltage was HALO (70%) and oxide growth temperature (45%) respectively. While the S/D Implantation was identified as an adjustment factor to get the nominal values of threshold voltage for PMOS and NMOS devices equal to -0.150V and +0.150V respectively.