A Fault Tolerant Adder Based On Alternative Computation

This paper presents a concurrent error correcting adder design employing fault tolerance through a duplication of a bit slice of a full adder based on alternative computation. The duplicated module is based on computing the sum and carry bits in two alternative ways so that faults will be detected by comparing the results (Sum and Carry out) obtained from the two computing paths. Redundancy is used to provide fail-operational functionality. If one hardware component goes down, then one of the redundant components can be brought in to continue operation of the system. The proposed method is simulated in standard CMOS 32nm technology and provides 11.11% saving in transistor count compared to a QMR (Quadruple Modular Redundancy) style design.