Studies on Sensitivity of Clock and Data Recovery Circuits to Power Supply Noise

This paper deals with the study of the impact of power supply noise on the performance of CMOS Clock and Data Recovery (CDR) Circuits. The sensitivity of the various blocks of the dual loop CDR circuit to power supply noise is rst studied and then it is demonstrated that insertion of suitable Low Dropout Regulators (LDOs) can enhance the performance of the CDR system with respect to power supply noise. Based on extensive simulations, it was observed that while the systemcan tolerate only about 20mV/10MHz noise on the power supply, incorporation of LDOs enables it to tolerate 200mV/10MHz noise without degradation in performance.