Dynamic Power Reduction of Stalls in Pipelined Architecture Processors

This paper proposes a technique for dynamic power reduction of pipelined processors. It is based on eliminating unnecessary transitions that are generated during the execution of NOP instructions. The approach includes the elimination of unnecessary changes in pipe register contents and the limitation of boundary movement of transitions caused by inevitable changes in pipe register contents due to insertion of a NOPinto a pipelined processor. To assess its efficiency, the proposed technique is applied to MIPS, DLX, and PAYEH processors considering a number of benchmarks. The experimental resultsshow that the techniques can lead to up to 10% reduction in thedynamic power consumption at a cost of negligible (almost zero)speed and (about 0.2%) area overheads.