THE STUDY OF VHDL BASED SYSTEM SPECIFICATION LANGUAGES
概念形成学习系统中数值属性的表示与聚类

Applying VHDL to support the design of embedded system is a way to extend VHDL to support system level design. In this paper, the authors observe several typical specification languages which supporting system level design, all the languages integrated VHDL into their methodologies. Based on the observation, the authors summarize the basic key points of a specification language which supporting system level design, and point out that combining formal methods with VHDL can produce an effective design assistant tool.