This paper proposes a novel hardware implementation of a dense recovery of stereovision 3D measurements. Traditionally 3D stereo systems have imposed the maximum number of stereo correspondences, introducing a large restriction on artificial vision algorithms. The proposed system-on-chip (SoC) provides great performance and efficiency, with a scalable architecture available for many different situations, addressing real time processing of stereo image flow. Using double buffering techniques properly combined with pipelined processing, the use of reconfigurable hardware achieves a parametrisable SoC which gives the designer the opportunity to decide its right dimension and features. The proposed architecture does not need any external memory because the processing is done as image flow arrives. Our SoC provides 3D data directly without the storage of whole stereo images. Our goal is to obtain high processing speed while maintaining the accuracy of 3D data using minimum resources. Configurable parameters may be controlled by later/parallel stages of the vision algorithm executed on an embedded processor. Considering hardware FPGA clock of 100 MHz, image flows up to 50 frames per second (fps) of dense stereo maps of more than 30,000 depth points could be obtained considering 2 Mpix images, with a minimum initial latency. The implementation of computer vision algorithms on reconfigurable hardware, explicitly low level processing, opens up the prospect of its use in autonomous systems, and they can act as a coprocessor to reconstruct 3D images with high density information in real time.
References
[1]
Arnbrosch, K.; Kubinger, W. Accurate hardware-based stereo vision. Comput. Vision Image Underst 2010, 114, 1303–1316, doi:10.1016/j.cviu.2010.07.008.
[2]
Diaz, J.; Ros, E.; Carrillo, R.; Prieto, A. Real-time system for high-image resolution disparity estimation. IEEE Trans. Image Process 2007, 16, 280–285, doi:10.1109/TIP.2006.884931. 17283786
[3]
Woodfill, J.I.; Buck, R.; Jurasek, D.; Gordon, G.; Brown, T. 3D vision: Developing an embedded stereo-vision system. Computer 2007, 40, 106–108.
[4]
Faugeras, O. Three-Dimensional Computer Vision: A Geometric Viewpoint; MIT Press: Cambridge, MA, USA, 1993.
[5]
Fusiello, A.; Irsara, L. Quasi-Euclidean epipolar rectification of uncalibrated images. Mach. Vision Appl 2011, 22, 663–670, doi:10.1007/s00138-010-0270-3.
[6]
Fusiello, A.; Trucco, E.; Verri, A. A compact algorithm for rectification of stereo pairs. Mach. Vision Appl 2000, 12, 16–22, doi:10.1007/s001380050120.
[7]
Moallem, P. Effective parameters in search space reduction used in a fast edge-based stereo matching. J. Circ. Syst. Comput 2005, 14, 249–266, doi:10.1142/S0218126605002349.
[8]
Cheng, L.A.; Gong, J.; Yang, X.; Fan, C.; Han, P. Robust affine invariant feature extraction for image matching. IEEE Geosci. Remote Sens. Lett 2008, 5, 246–250, doi:10.1109/LGRS.2008.915599.
[9]
Perri, S.; Colonna, D.; Zicari, P.; Corsonello, P. SAD-Based Stereo Matching Circuit for FPGAs. Proceedings of (ICECS ‘06): 13th IEEE International Conference on Electronics, Circuits and Systems, Calabria, Italy, 10–13 December 2006; pp. 846–849.
[10]
Park, D.-K.; Cho, H.-M.; Cho, S.-B.; Lee, J,-H. A Fast Motion Estimation Algorithm for SAD Optimization in Sub-Pixel. Proceedings of (ISIC ‘07): International Symposium on Integrated Circuits, Ulsan, South Korea, 26–28 September 2007; pp. 528–531.
[11]
Kalomiros, J.A.; Lygouras, J. Hardware implementation of a stereo co-processor in a medium-scale field programmable gate array. IET Comput. Digit. Tech 2008, 2, 336–346, doi:10.1049/iet-cdt:20070147.
[12]
Kalomiros, J.A.; Lygouras, J. Design and evaluation of a hardware/software FPGA-based system for fast image processing. Microprocess. Microsyst 2008, 32, 95–106, doi:10.1016/j.micpro.2007.09.001.
[13]
Banz, C.; Hesselbarth, S.; Flatt, H.; Blume, H.; Pirsch, P. Real-Time Stereo Vision System Using Semi-Global Matching Disparity Estimation: Architecture and FPGA-Implementation. Proceedings of 2010 International Conference on Embedded Computer Systems (SAMOS), Hannover, Germany, 19–22 July 2010; pp. 93–101.
[14]
Jia, Y.; Zhang, X.; Li, M.; An, L. A Miniature Stereo Vision Machine (MSVM-III) for Dense Disparity Mapping. Proceedings of (ICPR 2004): 17th International Conference on Pattern Recognition, Beijing, China, 23–26 August 2004; pp. 728–731.
[15]
Hariyama, M.; Yokoyama, N.; Kameyama, M.; Kobayashi, Y. FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture. Proceedings of 48th Midwest Symposium on Circuits and Systems, Miyagi, Japan, 7–10 August 2005; pp. 1219–1222.
[16]
Lee, S.H.; Yi, J.; Kim, J.S. Real-time stereo vision on a reconfigurable system. Lect. Notes Comput. Sci 2005, 3553, 225–236.
[17]
Perri, S.; Colonna, D.; Zicari, P.; Corsonello, P. SAD-Based Stereo Matching Circuit for FPGAs. Proceedings of (ICECS ‘06): 13th IEEE International Conference on Electronics, Circuits and Systems, Calabria, Italy, 10–13 December 2006; pp. 846–849.
[18]
Cuadrado, C.; Zuloaga, A.; Martin, J.L.; Lazaro, J.; Jimenez, J. Real-Time Stereo Vision Processing System in a FPGA. Proceedings of (IECON 2006): IEEE 32nd Annual Conference on Industrial Electronics, Bilbao, Spain, 6–10 November 2006; pp. 3455–3460.
[19]
Naoulou, A.; Boizard, J.-L.; Fourniols, J.Y.; Devy, M. An Alternative to Sequential Architectures to Improve the Processing Time of Passive Stereovision Algorithms. Proceedings of (FPL ‘06): International Conference on Field Programmable Logic and Applications, Toulouse, France, 28–30 August 2006; pp. 1–4.
[20]
Ibarra-Manzano, M.A.; Almanza-Ojeda, D.-L.; Devy, M.; Boizard, J.-L.; Fourniols, J.-Y. Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource Optimization. Proceedings of (DSD ‘09): 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, Toulouse, France, 27–29 August 2009; pp. 799–805.
[21]
Kim, J.; Kim, J.H.; Ho, H.H.; Cho, J.D. Real-Time Smoothing Filter for Three Dimensional Disparity Map Algorithm and Hardware Implementation. Proceedings of (MWSCAS): 2011 IEEE 54th International Midwest Symposium on Circuits and Systems, Suwon, South Korea, 7–10 August 2011; pp. 1–4.
[22]
Bariamis, D.; Iakovidis, D.K.; Maroulis, D. Dedicated hardware for real-time computation of second-order statistical features for high resolution images. Adv. Concepts Intell. Vision Syst. Proc 2006, 4179, 67–77.
[23]
Kim, J.; Sikora, T. Confocal Disparity Estimation and Recovery of Pinhole Image for Real-Aperture Stereo Camera Systems. Proceedings of (ICIP 2007): IEEE International Conference on Image Processing, Berlin, Germany, 16 September–19 October 2007; pp. V-229–V-232.
[24]
Ben-Ari, R.; Sochen, N. A geometric approach for regularization of the data term in stereo-vision. J. Math. Imag. Vision 2008, 31, 17–33, doi:10.1007/s10851-008-0066-5.
