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OALib Journal期刊
ISSN: 2333-9721
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Pipeline Hardware Design and Optimization for H.264 Deblocking Filter
H.264去块滤波的流水线结构硬件设计与优化

Keywords: FPGA,H,264,Deblocking filter,Pipeline
FPGA
,H.,264,去块滤波器,流水线

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Abstract:

With respect to the bottlenecks of H. 264 deblocking filter, which involve considerable volume of intermediate data and unagrecable processing speed, an optimization for pipclincbased deblocking filter was proposed. In the course of design for it, the processing sequence and datapath were optimized, then the intermediate data were filtered timely,thereby reducing the hardware resources for storage of them and cutting down the clock cycles for deblocking filter,while advancing the processing speed. Via the experiments of hardware implementation, the results demonstrate that the proposed deblocking filter is able to limit the block effect, accelerate the processing, while meeting the requirement of few hardware resources for high-definition video.

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