A VLSI Architecture Design of 9/7 and 5/3 DWT Filter for JPEG2000
一种用于JPEG2000的小波变换VLSI结构设计方法

A uniform 9/7 and 5/3 DWT filter by lifting scheme is proposed for JPEG2000.This paper also proposes a control method of row and column parallel filtering with minimum five lines cache.This architecture can achieve higher hardware utilization and lower temporary data storage without losing precision.By using this architecture,we have accomplished the hardware design.The algorithm is described by Verilog HDL,and simulated by modelsim.It is implemented by cyclone2-EP2C35FC672 under Altera DE2 board with Quartus 6.0.