A Frame Buffer Architecture Design for Fast Generating 3 D Graphics System
一种快速产生 3D 图形系统的帧存储器设计

This paper discusses a frame buffer architecture,in which,three parallel techniques (SIMD,Memory cross and Pipeline)and CACHE are used to improve the bandwidth of frame buffer.The proposed system permits parallel access to an N /2 pixels rectangle.The rectangle can be a row,a column or an array.Z buffer of the system can improve the efficience of hidden surface algorithm.