Two level core test compression based on partial test vector reuse and VRL coding
基于部分向量复用和变游程编码的二级SoC测试压缩

This paper presents a novel scheme for core based SoC test compression. All the test vectors belonging to distinct test sets are partially overlapped to form shorter overlapped vectors. Variable-Run-Length coding is utilized to further compress the result overlapped test vectors. Due to the fact that test application time is proportional to the length of the overlapped vector, except that the length of the overlapped vector is far less than the sum of the length of the original individual test vectors, minimal test application time can be obtained. Maximized compression ratio is realized through variable-Run-length coding. Experimental results indicate that the proposed method achieves reduced test application time and significant compression rate.