CAVLC coding algorithm and FPGA realization of high-speed entropy encoder
CAVLC编码算法及高速熵编码器的FPGA实现

Context-Based Adaptive Variable-Length Coding (CAVLC) algorithm was adopted as an entropy coding method in baseline and extended profile of H.264/AVC standard, but the detailed syntax on which was not explicitly stipulated. A profound analysis on the CAVLC coding algorithm of H.264 standard was performed based on the principle of CALVC decoding method. A high-speed and low power-consumption CAVLC coder for H.264/AVC standard was presented according to the former analysis, in which multi-clock domain processing and parallel processing techniques were adopted to improve the performance of the system, and arithmetic were used to replace some static code table to reduce memory consumption. The detailed design and FPGA realization method on each sub-blocks are also concerned. Finally, FPGA verification and realization indicates that the maximum coding system clock can up to 107.97MHz, and the coding delay is less than 36 clock cycles, which can adequately meet the needs of some high-definition and real-time applications.