VLSI architecture for 2-dimensional discrete wavelet transform with high performance and low memory
二维离散小波变换高效低存储VLSI架构设计*

This paper proposed a new high-performance and memory-efficient 2D DWT architecture with the modified lifting algorithm. It could effectively reduce the memory requirement by eliminating the transposing buffer. For an N×N image, only required 2N internal buffer for 5/3 DWT and required 4N for 9/7 DWT to perform 2D DWT with the critical path of one multiplier delay. Compared with the 2D DWT architectures existed, the architecture eliminated the transposing buffer between the row processor and the column processor and also adopted the folding and the pipeline technique to reduce the hardware resource and shorten the critical path.