Functional coverage driven verification for TAU/MVBC
功能覆盖率驱动的TAU/MVBC模块验证*

This paper describes a functional coverage driven verification environment for TAU/MVBC. According to the verification methodology manual (VMM) for System Verilog, a layered reusable verification environment was developed together with a final coverage report summary. Constrained random stimulus generation technique was applied to narrow down the input vector space and to improve functional coverage in a reasonable time. Assertions were utilized to cover function points which could rarely be covered by random combinations of input signals. The practice results show that the coverage driven verification technique can efficiently improve the verification efficiency by deliberately increasing the occurrence chance of the small probability event.