Multi-layer random stimulus strategy for microprocessor verification
一种面向微处理器验证的分层随机激励方法*

To address the increasing complexity of microprocessor function verification, this paper presented a new multiple-layer constraint random stimulation generation strategy. Multi-layer constraints from four layers, test, scenario, function and command, could strengthen the controllability on random stimulus generation in different granularities, and refine the stimulus space to speed up the whole verification work. Moreover, based on those fundamental functional behavior units of microprocessor, proposed a new configurable function library to generate two kinds of random stimulus for internal logic function and external communication interface respectively with better reusability for series processor verification. As shown in CKCore microprocessor verification experiments, compare with traditional constraint random stimulus generation, the proposed strategy can effectively improve the quality and efficiency of microprocessor verification, with 60% stimulus coding reduction, while more than 10% and 5% function and code coverage increase.