A FPGA Design of Bit-plane Coding for JPEG 2000
JPEG 2000系数位平面编码的FPGA设计*

FPGA implementation of the bit-plane coding in JPEG 2000 standard is studied in the paper. A architecture suitable for ASIC implementation is proposed ,which greatly speeds up the coding process and achieves higher hardware utilization, solve the problem how to read and write the coefficient state words in the RAMS, and decreases the frequency of the system to visit the coefficient state words in the RAMS. In this paper, cleanup pass works concurrently with magnitude refinement pass, which reduces the processing time by more than 30% compared with the conventional design. The design is simulated and verified on FPGA.