This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and negative boosted voltage levels of the boosted nodes, thus improving boosting efficiency and enhancing driver switching speed. Measured performance from test chips implemented with UMC 65？nm low-power CMOS technology (VTN ≈ VTP ≈ 0.5 V) indicates that the proposed driver provides a rising-delay improvement of 37%–50% and a falling-delay improvement of 25%–47% at 0.3？V for a loading ranging from a 0 to 24 mm long M6 metal line compared with the conventional bootstrapped driver. Although designed and optimized for subthreshold ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at higher nearly-threshold supply voltage as well. The proposed driver provides a rising delay improvement of 20% to 52% and a falling delay improvement of 23%–43% for VDD ranging from 0.3？V to 0.5？V, while consuming about 15% less average power than the conventional bootstrapped driver driving a 16？mm long M6 wire.
References
[1]
Wang, A.; Chandrakasan, A.; Kosonocky, D. Optimal Supply and Threshold Scaling for Sub-threshold CMOS Circuits. In Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, USA, 25–26 April 2002; Volume 4, pp. 5–9.
[2]
Wang, A.; Calhoun, B.H.; Chandrakasan, A. Sub-Threshold Design for Ultra Low-Power Systems; Springer: New York, NY, USA, 2008.
[3]
Lou, J.H.; Kuo, J.B. 1.5 V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI. IEEE J. Solid State Circuits 1997, 32, 119–121, doi:10.1109/4.553191.
Lu, H.W.; Su, C.C.; Liu, C.N. A Scalable Digitalized Buffer for Gigabit I/O. IEEE Trans. Circuits Syst. II Express Br. 2008, 55, 1026–1030, doi:10.1109/TCSII.2008.925661.
[6]
Chen, P.C.; Kuo, J.B. Sub-1 V CMOS large capacitive-load driver circuit using direct bootstrap technique for low-voltage CMOS VLSI. Electron. Lett. 2002, 38, 265–266, doi:10.1049/el:20020208.
[7]
Garcia, J.C.; Montiel-Nelson, J.A.; Nooshabadi, S. A Single-capacitor bootstrapped power-efficient CMOS driver. IEEE Trans. Circuits Syst. II Express Br. 2006, 53, 877–881, doi:10.1109/TCSII.2006.880337.
[8]
Chong-Fatt, L.; Kiat-Seng, Y.; Rofail, S.S. Sub-1 V bootstrapped CMOS driver for giga-scale-integration era. Electron. Lett. 1999, 35, 392–394, doi:10.1049/el:19990248.
[9]
Kil, J.; Gu, J.; Kim, C.H. A High-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive Boosting. IEEE Trans. Very Large Scale Integr. VLSI Syst. 2008, 16, 456–465.
[10]
Kim, J.W.; Kong, B.S. Low-voltage bootstrapped CMOS drivers with efficient conditional bootstrapping. IEEE Trans. Circuits Syst. II Express Br. 2008, 55, 556–560, doi:10.1109/TCSII.2007.916843.
[11]
Lu, C.Y.; Chuang, C.T. Energy efficient bootstrapped CMOS large RC-load driver circuit for ultra low-voltage VLSI. In Proceedings of the IEEE International Symposium on VLSI DesignAutomationand Test (VLSI-DAT), Hsinchu, Taiwan, 26–29 April 2010; pp. 70–73.
[12]
Tran, C.Q.; Kawaguchi, H.; Sakurai, T. Low-power high-speed level shifter design for block-level dynamic voltage scaling environment. In Proceedings of the 2005 International Conference on Integrated Circuit Design and Technology (ICICDT 2005), Austin, TX, USA, 9–11 May 2005; Volume 35, pp. 229–232.
