High Performance SDRAM Controller Design for HDTV Video Decoder
用于HDTV视频解码器的高性能SDRAM控制器

A high performance SDRAM controller for HDTV video decoder is proposed. Configured with multiple ports and integrated with an arbitration function, the SDRAM controller proposed can be used in place of traditional structures of bus DMA to share the bandwidth resource of the SDRAM among several function blocks in the HDTV decoder. The SDRAM controller consists of pipelined address path and data path, which take advantage of the pipeline feature of the SDRAM to enable the controller to process access requests from each port continuously, so that the storage volume of on-chip memories is significantly reduced. The simulation results show that up to 70% of the on-chip memories could be reduced compared to the traditional bus DMA structures, while the performance for HDTV decoding is assured.