Full well capacity and quantum efficiency optimization for small size backside illuminated CMOS image pixels with a new photodiode structure
一种用于优化小尺寸背照式CMOS图像传感器满阱容量与量子效率的新型光电二极管结构

To improve the full well capacity (FWC) of a small size backside illuminated (BSI) CMOS image sensor (CIS), the effect of photodiode capacitance (CPD) on FWC is studied, and a reformed pinned photodiode (PPD) structure is proposed. Two procedures are implemented for the optimization. The first is to form a varying doping concentration and depth stretched new N region, which is implemented by an additional higher-energy and lower-dose N type implant beneath the original N region. The FWC of this structure is increased by extending the side wall junctions in the substrate. Secondly, in order to help the enlarged well capacity achieve full depletion, two step P-type implants with different implant energies are introduced to form a P-type insertion region in the interior of the stretched N region. This vertical inserted P region guarantees that the proposed new PD structure achieves full depletion in the reset period. The simulation results show that the FWC can be improved from 1289e- to 6390e-, and this improvement does not sacrifice any image lag performance. Additionally, quantum efficiency (QE) is enhanced in the full wavelength range, especially 6.3% at 520 nm wavelength. This technique can not only be used in such BSI structures, but also adopted in an FSI pixel with any photodiode-type readout scheme.