A low power CMOS 3.3 Gbps continuous-time adaptive equalizer for serial link
一种用于3.3Gbps低功耗高速互连的连续时间自适应模拟均衡器*

This paper describes a high speed continuous-time analog adaptive equalizer as the front-end of receiver for high speed serial interface, which is compliant to many serial communication specifications such as USB2.0, PCI-E2.0, Rapid IO. The low and high frequency loops are merged to decrease the effect of delay between the two paths, in addition, the infinite input impedance facilitate the cascade stages to improve the boosting gain of high frequency. The implemented circuit architecture could facilitate the wide frequency range from 1Gbps to 3.3Gbps with different length FR4-PCB traces, which brings as much as 25dB loss. The replica control circuits are injected to give a convenient way to regulate common-mode voltage for full differential operation, besides, the ac coupling are adopted to suppress the common input from the forward stage. A prototype chip was fabricated in 0.18-um 1P6M mixed-signal CMOS technology. The actual area is 0.6 0.57 mm2, the analog equalizer operates up to 3.3Gbps over FR4-PCB trace with 25dB loss. The overall power dissipation is approximately 23.4mW.