Challenges of Process Technology in 32nm Technology Node
32nm CMOS工艺技术挑战

According to the international technology roadmap for semiconductors (ITRS),32nm technology node will be introduced around 2009.Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers.Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing.This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas:extension of immersion lithography,mobility enhancement substrate technology,metal/high-k (MHK) gate stack,ultra-shallow junction (USJ) and other strain enhancement engineering methods,including stress proximity effect (SPT),dual stress liner (DSL),stress memorization technique (SMT),high aspect ratio process (HARP) for STI and PMD,embedded SiGe (for pFET) and SiC (for nFET) source/drain (S/D) using selective epitaxial growth (SEG) method,metallization for middle of line (MOL) and back-end of line (BEOL),and ultra low-k (ULK) integration.