High Speed Multilevel Staged Clock Routing
高速多级时钟网布线

Clock routing is one of major steps in high performance driven layout design under deep sub micron technology. Buffered clock tree construction is a key factor for clock routing. A novel buffered clock routing algorithm is proposed. The strategy is to perform buffer insertion and placement according to clock sink distribution before clock net routing, and to optimize clock tree topology generation, detailed embedding following the buffer insertion process. The influence of the placed buffers on routing will be significantly reflected. The experimental results show that buffer pre\|placement will avoid blind routing in a great extent and achieve the balance of sub\|tree delay and load capacitance efficiently.