Simulation of Gate-All-Around Cylindrical Transistors for Sub-10 Nanometer Scaling
适用于按比例缩小至亚10nm的圆柱体全包围栅场效应管仿真

A gate-all-around cylindrical (GAAC) transistor for sub-10nm scaling is proposed.The GAAC transistor device physics,TCAD simulation,and proposed fabrication procedure are reported for the first time.Among all other novel FinFET devices,the gate-all-around cylindrical device can be particularly applied for reducing the problems of the conventional multi-gate FinFET and improving the device performance and the scale down capability.According to our simulation,the gate-all-around cylindrical device shows many benefits over conventional multi-gate FinFET,including gate-all-around rectangular (GAAR) devices.With gate-all-around cylindrical architecture,the transistor is controlled by an essentially infinite number of gates surrounding the entire cylinder-shaped channel.The electrical integrity within the channel is improved by reducing the leakage current due to the non-symmetrical field accumulation such as the corner effect.The proposed fabrication procedures for devices having GAAC device architecture are also discussed.The method is characterized by its simplicity and full compatibility with conventional planar CMOS technology.