Simulation study on short channel double-gate junctionless field-effect transistors
关于短沟道双栅无结型晶体管的仿真研究

We study the characteristics of short channel double-gate (DG) junctionless (JL) FETs by device simulation. Output I-V characteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed. Distributions of electron concentration, electric field and potential in the body channel region are also analyzed. Comparisons with conventional inversion-mode (IM) FETs, which can demonstrate the advantages of JL FETs, have also been performed.