A Slice Analysis-Based Bayesian Inference Dynamic Power Model for CMOS Combinational Circuits
基于切片分析的CMOS组合电路贝叶斯动态功耗模型

To improve the accuracy and speed in cycle-accurate power estimation,this paper uses multiple dimensional coefficients to build a Bayesian inference dynamic power model.By analyzing the power distribution and internal node state,we find the deficiency of only using port information.Then,we define the gate level number computing method and the concept of slice,and propose using slice analysis to distill switching density as coefficients in a special circuit stage and participate in Bayesian inference with port information.Experiments show that this method can reduce the power-per-cycle estimation error by 21.9% and the root mean square error by 25.0% compared with the original model,and maintain a 700+ speedup compared with the existing gate-level power analysis technique.