On modeling the digital gate delay under process variation
工艺浮动下数字门电路延时建模研究

Block based statistical static timing analysis (SSTA), being a promising technique to solve the timing issue of digital designs under process variation, demands gate delay models in specific forms. While most researches assumed the existence of such models without further discussion, to extract those prerequisite models for a complete digital library is by no means a trivial task. To achieve a characterization method with neither unacceptably poor accuracy nor forbiddingly high cost, we found that general-purposed gate delay models are useful as intermediaries between the circuit simulation data and the gate delay models in required forms. In this work, two gate delay models for process variation considering different driving and loading conditions are proposed. From the testing results, those models, especially the one that combines effective dimension reduction (EDR) from statistics society with comprehensive gate delay models, offer good accuracy with low characterization cost, and are thus competent for the use in SSTA. Besides, those models are of their own value in other SSTA techniques.