Patterned Dual pn Junctions Restraining Substrate Loss of an On-Chip Inductor
放射状双pn结抑制片上电感衬底损耗（英文）

Dual pn junctions in lateral and vertical directions are formed by diffusing the p~ on the patterned n-well in standard CMOS technology,which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor.The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated.For the first time,through the grounded p~ -diffusion layer shielding the substrate from the electric field of the inductor,the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n-wells.The quality factor is improved or reduced with the thickness of high resistance by 19%.This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor.