New Architecture of Accurate Clock Generator in IC Test System
IC测试系统精密定时器的新结构

A new structure of accurate clock generate subsystem is presented which is fit for VLSI design.The timing counter is divided into two parts,one for high speed and the other for low speed.Registers in low speed part are replaced by centralized memories,which decrease the wiring complexity and reduce the cost.Programmable counter and peripheral control circuits are designed to solve the problem of timing in incomplete period.The new clock generator can work at 100MHz and the total timing period can be up to more than 1h.