Improving Detectability of Resistive Shorts in FPGA Interconnects

The behavior of resistive short defects in FPGA interconnects is investigated through simulation and theoretical analysis.The results show that these defects result in timing failures and even Boolean faults for small defect resistance values.The best detection situations for large resistance defect happen when the path under test makes a v-to-v′ transition and another path causing short faults remains at value v.Small defects can be detected easily through static analysis.Under the best test situations,the effects of supply voltage and temperature on test results are evaluated.The results verify that lower voltage helps to improve detectability.If short material has positive temperature coefficient,low temperature is better;otherwise,high temperature is better.