Structure Design and Film Process Optimization for Metal_Gate Stress in 20nm nMOS Devices
20纳米nMOS器件中应力金属栅结构设计与薄膜工艺优化

MGS is one of key process-induced-strain (PIS) technologies for up-to-date CMOS integrations. In this paper, the optimizations to metal gate structure and film process were extensively investigated for great Metal-Gate Stress (MGS) in 20nm High-k/Metal-Gate-last (HK/MG-last) nMOS devices. The characteristics of advanced MGS technologies on device performances were studied through a process and device simulation by TCAD tools. The metal gate electrode with different stress values (0GPa~-6GPa) was implemented into the device simulation along with other traditional PIS technologies like e-SiC and nitride capping layer. The MGS demonstrated a great enhancing effect on channel carriers transporting in device as device pitch scaling down. In addition, the novel structure for tilted gate electrode was proposed and relatiohships between the tilt angle and channel stress was investigated. Also with a new method of Fully Stressed Replacement Metal Gate (FSRMG) and using plane-shape-HfO to substitute U-shape-HfO, the effect of MGS was improved. For greater film stress in metal gate, the process conditions for Physical Vapor Deposition (PVD) TiNx were optimized. The maxmium compressive stress of -6.5GPa TiNx was achieved with thinner film, greater RF power as well as about 6sccm N ratio.