An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process
An ultra-low-power 1Kb Sub-threshold SRAM in 180nm CMOS Process

This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure. Final test results verify the function of the SRAM. The minimal operating voltage of the chip is 350 mV, where the speed is 165 kHz, the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC.