Design and Synthesis of HDL Code Based on High Level FPGA Design Flow for SDR Model

There has been considerable recent interest in defining a Hardware Abstraction Layer (HAL) to facilitate code reuse in the signal processing subsystems of software-defined radios. HDL for FPGA-based signal processing is a significant aspect of such HAL efforts. In this study, we show how a platform-based approach to FPGA design that provides a high level of design abstraction can also provide the ability to target multiple FPGA families from a single source model. The approach combines direct mapping of a Simulink model with code generation of register-transfer level HDL. By exploiting retiming and other optimizations available through logic synthesis, it is possible to obtain very efficient realizations of signal processing functions. This research complements HAL recommendations by focusing on mechanisms, guidelines and methodologies for constructing signal processing functions in FPGAs. It helps to address requirements for executable specifications as well as providing source that can be compiled though automatic code generation. At last, this new design technique would help in designing and realizing SDR-3G wireless communication system and accelerate the transition to 4G wireless communication system.