Electronic Transport Properties of Junctionless Lateral Gate Silicon Nanowire Transistor Fabricated by Atomic Force Microscope Nanolithography

We present the fabrication, electrical characteristics, and effect of lateral gates in a junctionless silicon nanowire transistor. The transistor uses silicon nanowire on silicon-on-insulator wafer fabricated with an atomic force microscope nanolithography technique. Using AFM nanolithography allows us to make a chemical contrast between locally oxidized part of the surface and unexposed surface. This chemical contrast affects as a mask and the active part of the device is finally obtained after two step etching. The structure is uniformly low-doped for source, drain, channel, and the lateral gates regions, and confirms the behavior of junctionless nanowire transistors. The output current is controlled by channel doping and mobility of carriers instead of gate capacitance and it basically uses bulk conduction instead of surface channel conduction. The fabricated device exhibits an on-off ratio of 2×106 and a subthreshold swing of 160 mV/decade.