Reliability and Retention of Floating Body RAM on Bulk FinFET

This paper assesses one Transistor Floating Body Random Access Memory (1T-FBRAM) in Bulk FinFET devices as a candidate for conventional DRAM replacement in the future technology nodes. For the cell operation, Bipolar Junction Transistor (BJT) programming is used. Reliability and retention time of the floating body effect are studied on different gate lengths, fin widths and for different programming biases. The degradation mechanisms during cycling are identified. The optimum number of cycles extracted (~109) is still far below the 1016 cycles expected. Long retention times are obtained; however, with the tail bit distribution below the 64ms DRAM specifications. Besides, the generated floating body takes place beneath the drain at the n+/p+ drain/ground-plane junction, which explains the long retention times by the large junctions area. Moreover, the floating body can be obtained only by leaving floating the bulk contact of the bulk FinFET cell, which makes its integration in a DRAM chip challenging. On the other hand, the bulk FinFET device shows a biristor like behaviour but featuring more options by the use of the gate to control the write and read.