Investigation of the Dimension Effects of Sub-30nm Multiple-Gate SOI MOSFETs by TCAD Simulation

In this paper we use the commercial semiconductor device simulator, Sentaurus, to simulate the electrical characteristics of sub-30nm multiple-gate (MG) silicon-on-insulator (SOI) MOSFETs. The gate configurations of the simulated MG SOI MOSFETs include: single-gate (SG), two kinds of double-gate (DG), triple-gate (TG), and gate-all-around (GAA). We examine the effects of the dimensions of the gate length, fin height, fin width, and the transport models for each gate configuration. The simulation results can serve as the guidelines of device design and they indicate that as the gate length scales down to 15 nm below, only GAA, TG, and DG configurations with specific fin cross-section dimensions can meet the device requirements.