A Continuous-Time Sigma-Delta Modulator with a Hybrid Loop Filter and Capacitive Feedforward

A continuous-time (CT) sigma-delta (ΣΔ) modulator clocked at 128 MHz with a hybrid active-passive loop filter is presented for WCDMA applications. The proposed 5th-order loop filter architecture mainly consists of two passive integrators and three active integrators. To erase the summation amplifier used in the chain of integrators with weighted feedforward summation (CIFF) topology, the capacitive feedforward structure is employed. In addition, local feedback resistors form the bridge-T network to reduce the chip area. The prototype chip is fabricated with TSMC 0.18 μm CMOS technology. Under the supply voltage of 1.8 V, measured results have achieved the best FOM of 2.67 pJ/conv, a dynamic range of 62 dB, a SNDR of 60.26 dB, an ENOB of 9.72 bit, IM3 of -48 dB and a power consumption of 9 mW over a 2 MHz signal bandwidth. Including pads, the chip area is 0.642 (1.07 x 0.6) mm2.