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Sampling Jitter in Audio A/D Converters

DOI: 10.2478/v10168-011-0055-3

Keywords: analog-to-digital converter (ADC), successive approximation register (SAR) ADC, sigma-delta (ΣΔ) ADC, sample-and-hold circuit, DT ΣΔ modulator, CT ΣΔ modulator, time jitter, aperture jitter, clock jitter, periodic clock jitter, signal-to-noise ratio (SNR)

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Abstract:

This paper provides an overview of the effects of timing jitter in audio sampling analog-to-digital converters (ADCs), i.e. PCM (conventional or Nyquist sampling) ADCs and sigma-delta (ΣΔ) ADCs. Jitter in a digital audio is often defined as short-term fluctuations of the sampling instants of a digital signal from their ideal positions in time. The influence of the jitter increases particularly with the improvements in both resolution and sampling rate of today's audio ADCs. At higher frequencies of the input signals the sampling jitter becomes a dominant factor in limiting the ADCs performance in terms of signal-to-noise ratio (SNR) and dynamic range (DR).

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