International Journal of Reconfigurable Computing - oalib

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International Journal of Reconfigurable Computing

ISSN Print: 1687-7195

ISSN Online:

主页: http://www.hindawi.com/journals/ijrc/

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Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing

Mariam Hoseini,Zhou Tan,Chao You,Mark Pavicic

High-Speed FPGA 10's Complement Adders-Subtractors

G. Bioul,M. Vazquez,J. P. Deschamps,G. Sutter

Selected Papers from ReconFig 2009 International Conference on Reconfigurable Computing and FPGAs (ReconFig 2009)

Lionel Torres,Viktor K. Prasanna

Selected Papers from SPL 2009: Programmable Logic and Applications

Elías Todorovich,Valentin Obac Roda

Selected Papers from SPL 2009: Programmable Logic and Applications

Elías Todorovich,Valentin Obac Roda

Selected Papers from ReconFig 2009 International Conference on Reconfigurable Computing and FPGAs (ReconFig 2009)

Lionel Torres,Viktor K. Prasanna

An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures

F. Redaelli,M. D. Santambrogio,S. Ogrenci Memik

Parallel Processor for 3D Recovery from Optical Flow

Jose Hugo Barron-Zambrano,Fernando Martin del Campo-Ramirez,Miguel Arias-Estrada

An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography

Xinyu Li,Omar Hammami

Pipeline FFT Architectures Optimized for FPGAs

Bin Zhou,Yingning Peng,David Hwang

Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings

Knut Wold,Chik How Tan

Answer Set versus Integer Linear Programming for Automatic Synthesis of Multiprocessor Systems from Real-Time Parallel Programs

Harold Ishebabi,Philipp Mahr,Christophe Bobda,Martin Gebser,Torsten Schaub

A Hardware Filesystem Implementation with Multidisk Support

Ashwin A. Mendon,Andrew G. Schmidt,Ron Sass

Analysis and Design of a Context Adaptable SAD/MSE Architecture

Arvind Sudarsanam,Aravind Dasu,Karthik Vaithianathan

A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems

Manuel Salda a,Emanuel Ramalho,Paul Chow

An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing

Christian Schuck,Bastian Haetzer,Jürgen Becker

A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications

H. Ho,V. Szwarc,T. Kwasniewski

Non-Power-of-Two FFTs: Exploring the Flexibility of the Montium TP

Marcel D. van de Burgwal,Pascal T. Wolkotte,Gerard J. M. Smit

Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs

Gabriel Caffarena,Juan A. López,Gerardo Leyva,Carlos Carreras,Octavio Nieto-Taladriz

Providing Memory Management Abstraction for Self-Reconfigurable Video Processing Platforms

Kurt Franz Ackermann,Burghard Hoffmann,Leandro Soares Indrusiak,Manfred Glesner

Software Toolchain for Large-Scale RE-NFA Construction on FPGA

Yi-Hua E. Yang,Viktor K. Prasanna

Reaction Diffusion and Chemotaxis for Decentralized Gathering on FPGAs

Bernard Girau,César Torres-Huitzil,Nikolaos Vlassopoulos,José Hugo Barrón-Zambrano

FPGA Interconnect Topologies Exploration

Zied Marrakchi,Hayder Mrabet,Umer Farooq,Habib Mehrez

An Adaptive Message Passing MPSoC Framework

Gabriel Marchesan Almeida,Gilles Sassatelli,Pascal Benoit,Nicolas Saint-Jean,Sameer Varyani,Lionel Torres,Michel Robert

OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms

Beno t Miramond,Emmanuel Huck,Fran ois Verdier,Amine Benkhelifa,Bertrand Granado,Thomas Lefebvre,Mehdi A chouch,Jean Christophe Prevotet,Yaset Oliva,Daniel Chillet,Sébastien Pillement

Reducing Reconfiguration Overheads in Heterogeneous Multicore RSoCs with Predictive Configuration Management

Stéphane Chevobbe,Stéphane Guyetant

Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware

Christophe Bobda,Kevin Cheng,Felix Mühlbauer,Klaus Drechsler,Jan Schulte,Dominik Murr,Camel Tanougast

A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime

Thilo Pionteck,Roman Koch,Carsten Albrecht,Erik Maehle

Multilevel Simulation of Heterogeneous Reconfigurable Platforms

Damien Picard,Loic Lagadec

A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation

Fernando Martín del Campo,René Cumplido,Roberto Perez-Andrade,A. G. Orozco-Lugo

vMAGIC—Automatic Code Generation for VHDL

Christopher Pohl,Carlos Paiz,Mario Porrmann

A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks

Jim Harkin,Fearghal Morgan,Liam McDaid,Steve Hall,Brian McGinley,Seamus Cawley

Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs

Shuli Gao,Dhamin Al-Khalili,Noureddine Chabini

Speeding Up FPGA Placement via Partitioning and Multithreading

Cristinel Ababei

Experiencing a Problem-Based Learning Approach for Teaching Reconfigurable Architecture Design

Erwan Fabiani

Hardware Accelerated Sequence Alignment with Traceback

Scott Lloyd,Quinn O. Snell

High level modeling of Dynamic Reconfigurable FPGAs

Imran Rafiq Quadri,Samy Meftali,Jean-Luc Dekeyser

A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip

Diana G hringer,Thomas Perschke,Michael Hübner,Jürgen Becker

A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips

Peter Zipf,Gilles Sassatelli,Nurten Utlu,Nicolas Saint-Jean,Pascal Benoit,Manfred Glesner

Selected Papers from ReConFig 2008

Lionel Torres,Cesar Torres

Selected Papers from ReCoSoC 2008

Michael Hübner,J. Manuel Moreno,Gilles Sassatelli,Peter Zipf

Selected Papers from SPL 2008: Programmable Logic and Applications

Gustavo Sutter,Richard Katz

Current Trends on Reconfigurable Computing

Jürgen Becker,Michael Hübner,Roger Woods,Philip Leong

A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC

Diego Puschini,Fabien Clermidy,Pascal Benoit,Gilles Sassatelli,Lionel Torres

Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation

Johan Ditmar,Steve McKeever,Alex Wilson

Dynamic Hardware Development

Stephen Craven,Peter Athanas

The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units

Chi Wai Yu,Julien Lamoureux,Steven J. E. Wilton,Philip H. W. Leong,Wayne Luk

An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Motoki Amagasaki,Ryoichi Yamaguchi,Masahiro Koga,Masahiro Iida,Toshinori Sueyoshi

On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

Y. Guillemenet,L. Torres,G. Sassatelli,N. Bruchon

SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication

Sami Boukhechem,El-Bay Bourennane

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