Multilevel k-way Hypergraph Partitioning

George Karypis,Vipin Kumar

Iterative Partitioning with Varying Node Weights

Andrew E. Caldwell,Andrew B. Kahng,Igor L. Markov

FPGA Partitioning with Complex Resource Constraints

Huiqun Liu,Kai Zhu,D. F. Wong

An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization

Chaeryung Park,Taewhan Kim,C. L. Liu

Design and Analysis of Digital Ratioed Compressors for Inner Product Processing

Chua-Chin Wang,Chenn-Jung Huang,Po-Ming Lee

Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library

Chua-Chin Wang,Chenn-Jung Huang,I-Yen Chang

Model-integrated Tools for the Design of Dynamically Reconfigurable Systems

Ted Bapty,Sandeep Neema,Jason Scott,Janos Sztipanovits,Sameh Asaad

Testing and Diagnosing Dynamic Reconfigurable FPGA

Chi-Feng Wu,Cheng-Wen Wu

Electro-thermal Modelling of Monolithic and Hybrid Microwave and Millimeter Wave IC's

W. Batty,A. J. Panks,R. G. Johnson,C. M. Snowden

A New Bus Assignment Algorithm for a Shared Bus Switch Fabric

D. Torres,J. Gonzalez,M. Guzman

Graphical Design Techniques for Fixed-point Multiplication

A. G. Dempster

Exact Output Response Computation of RC Interconnects Under General Polynomial Input Waveforms

L. M. Patnaik,Satrajit Gupta

A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop

Chua-Chin Wang,Yu-Tsun Chien,Ying-Pei Chen

Analytical and Computational Advances for Hydrodynamic Models of Classical and Quantum Charge Transport

Joseph W. Jerome

νMOS-based Sorter for Arithmetic Applications

E. Rodríguez-Villegas,M. J. Avedillo,J. M. Quintana,G. Huertas,A. Rueda

The Chapman-Enskog Expansion and the Quantum Hydrodynamic Model for Semiconductor Devices

Carl L. Gardner,Christian Ringhofer

Layout Modeling and Design Space Exploration in Pss1 System

Fur-Shing Tsai,Yu-Chin Hsu

IDDQ Testing Experiments for Various CMOS LogicDesign Structures

A. Toukmaji,R. Helms,R. Makki,W. Mikhail

Datapath Optimization Using Layout Information: An Empirical Study

Allen C.-H. Wu

RT Component Sets for High-Level Design Applications

Nikil D. Dutt,Pradip K. Jha

Statistical Module Level Area and Delay Estimation

Akhilesh Tyagi

Current Testing of CMOS Combinational Circuits withSingle Floating Gate Defects

Victor H. Champac,Joan Figueras

IDDQ Detectable Bridges in Combinational CMOS Circuits

E. Isern,J. Figueras

Taking Thermal Considerations Into Account DuringHigh-Level Synthesis

Jen-Pin Weng,Alice C. Parker

Application of Dynamic Supply Current Monitoring toTesting Mixed-Signal Circuits

Mahmoud A. Al-Qutayri,Peter R. Shepherd

Module Selection in Microarchitectural Synthesis forMultiple Critical Constraint Satisfaction

Ian G. Harris,Alex Orailoğlu

Linking Behavioral, Structural, and Physical Modelsof Hardware

Fadi J. Kurdahi

Advancements in Power Supply Current Testing

Rafic Z. Makki

Combining Technology Mapping With Layout

Massoud Pedram,Narasimha Bhat,Ernest S. Kuh

Effective Coupling Between Logic Synthesis and LayoutTools for Synthesis of Area and Speed-Efficient Circuits

Mandalagiri S. Chandrasekhar,Robert H. McCharles,David E. Wallace

A Timing-Driven Partitioning System for Multiple FPGAs

Kalapi Roy,Carl Sechen

Switch-level Differential Fault Simulation of MOS VLSI Circuits

Evstratios Vandris,Gerald Sobelman

Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation

Srilata Raman,C. L. Liu,Larry G. Jones

On Generating Optimal Signal Probabilities for Random Tests: A Genetic Approach

M. Srinivas,L. M. Patnaik

A New Theory for Testability-Preserving Optimization ofCombinational Circuits

Jiabi Zhu,Mostafa Abd-El-Barr,Carl McCrosky

Fault Modeling of ECL for High Fault Coverage of Physical Defects

Sankaran M. Menon,Yashwant K. Malaiya,Anura P. Jayasumana

Guest Editorial

Sunil R. Das

Design of an ASIC Chip for Skeletonization of Graylevel Digital Images

B. Majumdar,V. V. Ramakrishna,P. S. Dey,A. K. Majumdar

An O(NlogN) Algorithm for Region Definition Using Channels/Switchboxes and Ordering Assignment

Jin-Tai Yan,Pei-Yung Hsiao

TOGAPS: A Testability Oriented GeneticAlgorithm For Pipeline Synthesis

C. P. Ravikumar,V. Saxena

A Multi-Terminal Net Router for Field-Programmable Gate Arrays

Dinesh Bhatia,Amit Chowdhary

Design and Implementation of a Low Power Ternary Full Adder

A. Srivastava,K. Venkatapathy

DP-FPGA: An FPGA Architecture Optimized for Datapaths

Don Cherepacha,David Lewis

Closed Form Aliasing Probability For Q-ary Symmetric Errors

Geetani Edirisooriya

A Fast Clustering-Based Min-Cut Placement AlgorithmWith Simulated-Annealing Performance

Youssef Saab

A Sea-of-Gates Style FPGA Placement Algorithm

Kalapi Roy,Bingzhong (David) Guan,Carl Sechen

Erratum

A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays

S. Bandyopadhyay,A. Sengupta,B. B. Bhattacharya

Behavioral Simulation and Performance Evaluation of Multi-Processor Architectures

Ausif Mahmood

Minimum-Cost Node-Disjoint Steiner Trees in Series-Parallel Networks

Sunil Chopra,Kalyan T. Talluri