VLSI Design - oalib

OALib Journal期刊
ISSN: 2333-9721
费用：99美元

投递稿件

为什么选择我们？ >>

- 开源期刊

- 同行审议

- 快速出刊

- 终身存储

- 免费检索

- 免费推广

- 更多...

- 搜索引擎

VLSI Design

ISSN Print: 1065-514X

ISSN Online:

主页: http://www.hindawi.com/journals/vlsi/

分享:

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

Usha Mehta,K. S. Dasgupta,N. M. Devashrayee

A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips

Guanyi Sun,Shengnan Xu,Xu Wang,Dawei Wang,Eugene Tang,Yangdong Deng,Sun Chan

Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

Yoni Aizik,Avinoam Kolodny

Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

Subhra Dhar,Manisha Pattanaik,Poolla Rajaram

A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies

Soumya Pandit,Chittaranjan Mandal,Amit Patra

CONTANGO: Integrated Optimization of SoC Clock Networks

Dong-Jin Lee,Igor L. Markov

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

Usha Mehta,Kankar Dasgupta,Niranjan Devashrayee

Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms

I. Hameem Shanavas,Ramaswamy Kannan Gnanamurthy

Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies

M. A. R. Chaudhry,Z. Asad,A. Sprintson,J. Hu

Shedding Physical Synthesis Area Bloat

Ying Zhou,Charles J. Alpert,Zhuo Li,Cliff Sze,Louise H. Trevillyan

The Impact of Statistical Leakage Models on Design Yield Estimation

Rouwaida Kanj,Rajiv Joshi,Sani Nassif

SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection

Debasri Saha,Susmita Sur-Kolay

CAD for Gigascale SoC Design and Verification Solutions

Shiyan Hu,Zhuo Li,Yangdong Deng

CAD for Gigascale SoC Design and Verification Solutions

Shiyan Hu,Zhuo Li,Yangdong Deng

Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs

Reza Hashemian

A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation

Sergio Saponara,Tommaso Baldetti,Luca Fanucci

A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

Akila Gothandaraman,Gregory D. Peterson,G. Lee Warren,Robert J. Hinde,Robert J. Harrison

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Tooraj Nikoubin,Poona Bahrebar,Sara Pouri,Keivan Navi,Vaez Iravani

Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey

Usha S. Mehta,Kankar S. Dasgupta,Niranjan M. Devashrayee

FPGA Implementation of an Amplitude-Modulated Continuous-Wave Ultrasonic Ranger Using Restructured Phase-Locking Scheme

P. Sumathi,P. A. Janakiraman

Post-CTS Delay Insertion

Jianchao Lu,Baris Taskin

Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators

JunKyu Lee,Gregory D. Peterson,Robert J. Harrison,Robert J. Hinde

Error Immune Logic for Low-Power Probabilistic Computing

Bo Marr,Jason George,Brian Degnan,David V. Anderson,Paul Hasler

A SiGe BiCMOS Instrumentation Channel for Extreme Environment Applications

Chandradevi Ulaganathan,Neena Nambiar,Kimberly Cornett,Robert L. Greenwell,Jeremy A. Yager,Benjamin S. Prothro,Kevin Tham,Suheng Chen,Richard S. Broughton,Guoyuan Fu,Benjamin J. Blalock,Charles L. Britton Jr.,M. Nance Ericson,H. Alan Mantooth,Mohammad M. Mojarradi,Richard W. Berger,John D. Cressler

A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

Jun Zhao,Yong-Bin Kim

An Approach for Implementing State Machines with Online Testability

P. K. Lala,A. Mathews,J. P. Parkerson

FPGA-Based Software Implementation of Series Harmonic Compensation for Single Phase Inverters

K. Selvajyothi,P. A. Janakiraman

CORDIC Architectures: A Survey

B. Lakshmi,A. S. Dhar

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

Yan Zhu,U-Fat Chio,He-Gong Wei,Sai-Weng Sin,Seng-Pan U,R. P. Martins

Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping

K. Odame,P. E. Hasler

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Kumar Yelamarthi,Chien-In Henry Chen

Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance

Yao Xu,Ashok Srivastava,Ashwani K. Sharma

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Saumil G. Merchant,Gregory D. Peterson

Selected Papers from the Midwest Symposium on Circuits and Systems

Gregory D. Peterson,Ethan Farquhar,Benjamin Blalock

Selected Papers from the Midwest Symposium on Circuits and Systems

Gregory D. Peterson,Ethan Farquhar,Benjamin Blalock

A New XOR Structure Based on Resonant-Tunneling High Electron Mobility Transistor

Mohammad Javad Sharifi,Davoud Bahrepour

Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Ramesh Vaddi,S. Dasgupta,R. P. Agarwal

A Multilevel Congestion-Based Global Router

Logan Rakai,Laleh Behjat,Shawki Areibi,Tamas Terlaky

Low-Cost Allocator Implementations for Networks-on-Chip Routers

Min Zhang,Chiu-Sing Choy

Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management

Faizal A. Samman,Thomas Hollstein,Manfred Glesner

Reduced Voltage Scaling in Clock Distribution Networks

Khader Mohammad,Ayman Dodin,Bao Liu,Sos Agaian

Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS

Peter Nilsson

Floorplan-Driven Multivoltage High-Level Synthesis

Xianwu Xing,Ching Chuen Jong

Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers

Rida Assaad,Jose Silva-Martinez

MEMS Switches and SiGe Logic for Multi-GHz Loopback Testing

D. C. Keezer,D. Minier,P. Ducharme,D. Viens,G. Flynn,J. McKillop

A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators

Tzung-Je Lee,Chua-Chin Wang

Design and Characterization of the Next Generation Nanowire Amplifiers

Sotoudeh Hamedi-Hagh,Ahmet Bindal

A Programmable Max-Log-MAP Turbo Decoder Implementation

Perttu Salmela,Harri Sorokin,Jarmo Takala

Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach

E. J. Peralías,M. A. Jalón,A. Rueda

Integrated VCOs for Medical Implant Transceivers

Ahmet Tekin,Mehmet R. Yuce,Wentai Liu

©2008-2020 OALib, Inc | Public user content licensed CC-BY 4.0 unless otherwise specified. OALib ISSN Online: 2333-9721 OALib ISSN Print: 2333-9705