The paper presents a unified hybrid architecture to compute the integer inverse discrete cosine transform (IDCT) of multiple modern video codecs—AVS, H.264/AVC, VC-1, and HEVC (under development). Based on the symmetric structure of the matrices and the similarity in matrix operation, we develop a generalized “decompose and share” algorithm to compute the IDCT. The algorithm is later applied to four video standards. The hardware-share approach ensures the maximum circuit reuse during the computation. The architecture is designed with only adders and shifters to reduce the hardware cost significantly. The design is implemented on FPGA and later synthesized in CMOS 0.18？um technology. The results meet the requirements of advanced video coding applications. 1. Introduction In recent years, different video applications use different video standards, such as H.264/AVC [1], VC-1 [2], and AVS [3]. To improve the coding efficiency further, recently a joint collaboration team on video coding (JCT-VC) is drafting a next generation video coding standards, known tentatively as high efficient video coding (HEVC or H.265) [4]. The target bit rate is half of that of H.264/AVC. Besides, several other effective techniques are proposed in the draft to reduce the complexity of the encoder such as improved intrapicture coding, and simpler VLC coefficients [5]. As a result of these new features, experts predict that the HEVC will dominate the future multimedia market. In order to meet up the present and future demands of different multimedia applications, it becomes necessary to develop a unified video decoder that can support all popular video standards on a single platform. In recent years, there is a growing interest to develop multistandard inverse transform architectures for advanced multimedia applications. However, most of them do not support AVS, the video codec developed by Chinese government that became the core technology of China Mobile Multimedia Broadcasting (CMMB) [6]. None of the existing works supports the HEVC; thought it is not finalized yet, considering the future prospective of the HEVC [7], it is important to start exploring possible implementation in hardware of the transform unit discussed in the draft. In this paper, we present a new generalized algorithm and its hardwire implementation of an 8 × 8 IDCT architecture. The scheme is based on matrix decomposition with sparse matrices and offset computations. These sparse matrices are derived in a way that can be reused maximum number of times during decoding different inverse matrices. All multipliers
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