oalib
Search Results: 1 - 10 of 100 matches for " "
All listed articles are free for downloading (OA Articles)
Page 1 /100
Display every page Item
Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA  [PDF]
Nilanka Rajapaksha,Amila Edirisuriya,Arjuna Madanayake,Renato J. Cintra,Dennis Onen,Ihab Amer,Vassil S. Dimitrov
Journal of Electrical and Computer Engineering , 2013, DOI: 10.1155/2013/834793
Abstract: Transformation and quantization play a critical role in video codecs. Recently proposed algebraic-integer-(AI-) based discrete cosine transform (DCT) algorithms are analyzed in the presence of quantization, using the High Efficiency Video Coding (HEVC) standard. AI DCT is implemented and tested on asynchronous quasi delay-insensitive logic, using Achronix SPD60 field programmable gate array (FPGA), which leads to lower complexity, higher speed of operation, and insensitivity to process-voltage-temperature variations. Performance of AI DCT with HEVC is measured in terms of the accuracy of the transform coefficients and the overall rate-distortion (R-D) characteristics, using HM 7.1 reference software. Results indicate a 31% improvement over the integer DCT in the number of transform coefficients having error within 1%. The performance of the 65?nm asynchronous hardware in terms of speed of operation is investigated and compared with the 65?nm synchronous Xilinx FPGA. Considering word lengths of 5 and 6 bits, a speed increase of 230% and 199% is observed, respectively. These results indicate that AI DCT can be potentially utilized in HEVC for applications demanding high accuracy as well as high throughput. However, novel quantization schemes are required to allow the accuracy improvements obtained. 1. Introduction High dynamic range (HDR) video and image transmission over digital communication channels is undergoing exponential growth [1]. With the increasing demand for high-definition programming, there exists a strong need for efficient digital video coding (DVC) that provides high data compression ratios which in turn leads to better utilization of network resources [2]. The H.264/AVC standard [3] does not provide the required compression ratios for emerging capture and display technologies such as ultra high definition (UHD) [4], multiview [5], and autostereoscopy [6]. To address such emerging needs, the Joint Collaborative Team on Video Coding (JCT-VC) has developed the successor for H.264/AVC, called High Efficiency Video Coding (HEVC) [4]. The HEVC standard aims at achieving a 50% reduction in data rate compared with its predecessors while maintaining low complexity computation. Video compression systems operating at high frequencies and resolutions require hardware capable of significant throughput with tolerable area and power requirements. Real-time video compression circuits having high numerical accuracy are needed for next-generation video [1], coding systems [2, 3, 7], and retina displays [8]. The two-dimensional (2D) 8 8 discrete cosine
Point DCT VLSI Architecture for Emerging HEVC Standard  [PDF]
Ashfaq Ahmed,Muhammad Usman Shahid,Ata ur Rehman
VLSI Design , 2012, DOI: 10.1155/2012/752024
Abstract: This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, up to , the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed architecture sustains real-time processing of 1080P HD video codec running at 150?MHz. 1. Introduction As the technology is evolving day by day, the size of hardware is shrinking with an increase of the storage capacity. High-end video applications have become very demanding in our daily life activities, for example, watching movies, video conferencing, creating and saving videos using high definition video cameras, and so forth. A single device can support all the multimedia applications which seemed to be dreaming before, for example, new high-end mobile phones and smart phones. As a consequence, new highly efficient video coders are of paramount importance. However, high efficiency comes at the expense of computational complexity. As pointed out in [1, 2], several blocks of video codecs, including the transform stage [3], motion estimation and entropy coding [4], are responsible for this high complexity. As an example the discrete-cosine-transform (DCT), that is used in several standards for image and video compression, is a computation intensive operation. In particular, it requires a large number of additions and multiplications for direct implementation. HEVC, the brand new and yet-to-release video coding standard, addresses high efficient video coding. One of the tools employed to improve coding efficiency is the DCT with different transform sizes. As an example, the 16-point DCT of HEVC is shown in [5]. In video compression, the DCT is widely used because it compacts the image energy at the low frequencies, making easy to discard the high frequency components. To meet the requirement of real-time processing, hardware implementations of 2-D DCT/inverse DCT (IDCT) are adopted, for example, [6]. The 2-D DCT/IDCT can be implemented with the 1-D DCT/IDCT and a transpose memory in a row-column decomposition manner. In the direct implementation of DCT, float-point multiplications have to be tackled, which cause precision problems in
Performance Comparison of AVS and H.264/AVC Video Coding Standards
Xin-Fu Wang,De-Bin Zhao,
Xin-Fu
,Wang,and,De-Bin,Zhao

计算机科学技术学报 , 2006,
Abstract: A new audio and video compression standard of China, known as advanced Audio Video coding Standard (AVS). is emerging. This standard provides a technical solution for many applications within the information industry such as digital broadcast, high-density laser-digital storage media, and so on. The basic part of AVS, AVS1-P2, targets standard definition (SD) and high definition (HD) format video compression, and aims to achieve similar coding efficiency as H.264/AVC but with lower computational complexity. In this paper, we first briefly describe the major coding tools in AVS1-P2, and then perform the coding efficiency comparison between AVS1-P2 Jizhun profile and H.264/AVC main profile. The experimental results show that the AVS1-P2 Jizhun profile has an average of 2.96% efficiency loss relative to H.264/AVC main profile in terms of bit-rate saving on HD progressive-scan sequences, and an average of 28.52% coding loss on interlace-scan sequences. Nevertheless, AVS1-P2 possesses a valuable feature of lower computational complexity.
A Design of Intra Predictor Supporting H. 264 and AVS
一种支持H.264和AVS的帧内预测器设计

XU Zhang-lei,ZHENG Shi-bao,YANG Yu-hong,
徐张磊
,郑世宝,杨宇红

中国图象图形学报 , 2007,
Abstract: To adapt the intra predictor in multi-standard video coder to H.264 and AVS stand,a configurable hardware architecture design of intra predictor that supports both H.264 and AVS was proposed based on the similarities bebween the intra prediction algorithms in both standards.This kind of architecture can implement most intra prediction algorithms in one configurable calculate unit and thus can reduce the use of chip area.In order to enhance the speed of process,four parallel configurable generator unit are adopted in our design.This design was synthesized and the result showed that this architecture occupied 10 371 LUTs on FPGA ane its frequency can be 150 MHz.
Fast Algorithm of Subband Discrete Cosine Transform Based on H.264
基于H.264的子带DCT快速算法

Jiang Jian-guo,Lu Xiao-hong,Qi Mei-bin,Zhan Shu,
蒋建国
,卢晓红,齐美彬,詹曙

电子与信息学报 , 2009,
Abstract: Fast DCT (Discrete Cosine Transform) is one of the key issues in H.264,according to the properties of DCT coefficients' energy distribution and the characteristics of"zigzag scan",one fast DCT algorithm is proposed based on divided subbands.In the algorithm,DCT coefficients of the prediction residue (Zero Quantized DCT coefficients,ZQDCT) are set zero predictably before implementing DCT and quantization (Q),and then the redundant computations are deduced greatly.One adaptive scheme is also presented with mu...
一种支持H.264和AVS的帧内预测器设计  [PDF]
徐张磊,郑世宝,杨宇红
中国图象图形学报 , 2007, DOI: 10.11834/jig.20071010
Abstract: 为了使多标准视频解码器中的帧内预测器能够支持H.264和AVS两种视频标准,在对H.264和AVS两标准中的帧内预测计算模式进行分析,并对各模式计算公式之间相似性进行分析的基础之上,提出了一种支持H.264和AVS两种标准的,可配置的帧内预测值计算硬件架构。该架构由于将大部分预测模式的计算放到一个可配置的计算单元中进行,从而大大减少了芯片资源的浪费。为了提高处理速度,可采用4个相同的可配置的计算单元并行计算,一次计算出4个像素点的预测值。实验结果表明,该硬件架构在FPGA上占用10371个LUTs,频率可以达到150MHz。
Prediction of Transformed (DCT) Video Coding Residual for Video Compression  [PDF]
Matthieu Moinard,Isabelle Amonou,Pierre Duhamel,Patrice Brault
Computer Science , 2014,
Abstract: Video compression has been investigated by means of analysis-synthesis, and more particularly by means of inpainting. The first part of our approach has been to develop the inpainting of DCT coefficients in an image. This has shown good results for image compression without overpassing todays compression standards like JPEG. We then looked at integrating the same approach in a video coder, and in particular in the widely used H264 AVC standard coder, but the same approach can be used in the framework of HEVC. The originality of this work consists in cancelling at the coder, then automatically restoring, at the decoder, some well chosen DCT residual coefficients. For this purpose, we have developed a restoration model of transformed coefficients. By using a total variation based model, we derive conditions for the reconstruction of transformed coefficients that have been suppressed or altered. The main purpose here, in a video coding context, is to improve the ratedistortion performance of existing coders. To this end DCT restoration is used as an additional prediction step to the spatial prediction of the transformed coefficients, based on an image regularization process. The method has been successfully tested with the H.264 AVC video codec standard.
Forward and inverse 2-D DCT architectures targeting HDTV for H.264/AVC video compression standard
Agostini,L.; Porto,R.; Porto,M.; Silva,T.; Rosa,L.; Güntzel,J.; Silva,I.; Bampi,S.;
Latin American applied research , 2007,
Abstract: this paper presents the architecture and the vhdl design of the integer two-dimensional discrete cosine transform (2-d dct) used in the h.264/avc codecs. the forward and inverse 2-d dct architectures were designed and their synthesis results mapped to altera fpgas are presented. the 2-d dct calculation is performed by exploring the separability property, in such way, each 2-d dct architecture is divided in two 1-d dct calculations that are joined through a transpose buffer. the 1-d dct transforms implemented and herein described are multiplierless, hence optimized shift-add operations are used. the architectures have a dedicated pipeline, optimized to process one input data per clock cycle. these architectures are able to cope with h.264/avc encoder or decoder requirements targeting high definition digital television (hdtv), with 1920x1080 pixel/frame at 30 frames per second.
Forward and inverse 2-D DCT architectures targeting HDTV for H.264/AVC video compression standard
L. Agostini,R. Porto,M. Porto,T. Silva
Latin American applied research , 2007,
Abstract: This paper presents the architecture and the VHDL design of the integer Two-Dimensional Discrete Cosine Transform (2-D DCT) used in the H.264/AVC codecs. The forward and inverse 2-D DCT architectures were designed and their synthesis results mapped to Altera FPGAs are presented. The 2-D DCT calculation is performed by exploring the separability property, in such way, each 2-D DCT architecture is divided in two 1-D DCT calculations that are joined through a transpose buffer. The 1-D DCT transforms implemented and herein described are multiplierless, hence optimized shift-add operations are used. The architectures have a dedicated pipeline, optimized to process one input data per clock cycle. These architectures are able to cope with H.264/AVC encoder or decoder requirements targeting High Definition Digital Television (HDTV), with 1920x1080 pixel/frame at 30 frames per second.
Research on DCT-based Video Encryption under H.264
H.264标准中基于DCT的视频加密研究

CAO Yi,ZHANG Rong,LIU Zheng-kai,
曹奕
,张荣,刘政凯

中国图象图形学报 , 2005,
Abstract: With the development of information science and the computer technology,the application of video in commerce on the Internet,such as video on demand or video on line has become more and more common.At the same time,the demand for security becomes more and more urgent.According to the characteristics of the latest video compression standard H.264,this paper proposes several DCT-based encryption algorithms,conducts simulation on two standard video sequences,and analyzes and compares the quality of those proposed algorithms.The experimental results show that the proposed algorithms have no impact on the compression efficiency and have gained good encryption results with low complexity.The simulation results are all tested on JM(joint model,version 7.3) reference software,which is especially programmed for testing the coding standard of H.264.
Page 1 /100
Display every page Item


Home
Copyright © 2008-2017 Open Access Library. All rights reserved.